Based on industry-leading Interlaken IP for chip-to-chip connectivity, the Die-to-Die IP portfolio targets chiplets and heterogeneous solutions to support monolithic and 2.5D based ASICs
SAN MATEO, Calif.--(BUSINESS WIRE)--OpenFive, the leading provider of customizable, silicon-focused solutions with differentiated IP, today announced the launch of a new Die-to-Die (D2D) interface IP portfolio to serve next-generation chiplet based designs for Networking, HPC, and AI Markets.
With recent advances in package technologies and the cost per area increase in newer nodes, it is advantageous to connect multiple dies, or chiplets, on a single package with silicon-based interposer or an organic substrate. To enable this heterogeneous integration for various markets, OpenFive Die-to-Die connectivity IP is a major enablement block. OpenFive’s 1st Generation Die-to-Die IP is specifically designed to provide a very low-latency controller to work with SerDes based connectivity between two dies. OpenFive Die-to-Die IP is intended to enable SoC architects to connect chip logic to optimized XSR/VSR/SR based SerDes while embracing native customer-defined interfaces, or Arm® AMBA® AXI.
OpenFive’s die-to-die controller uniquely offers low latency and scalable throughput to address very high-bandwidth requirements in the multi terabits range with a single controller. Optional low latency FEC (Forward Error Correction) IP Engines can help achieve very low bit error rates (BER) depending on the characteristics of the channel connecting the two dies.
“We have achieved a throughput of up to >2Tbps and latency of few tens of nano-seconds end to end with a lead customer in HPC,” said Mohit Gupta, SVP and General Manager, IP Business Unit, OpenFive. “Additionally, working with our leading SerDes partners, we can offer a complete sub-system solution optimized for their needs.”
OpenFive is uniquely positioned with over a decade of experience in providing solutions for leading networking, storage, and AI products with its Interlaken IP for Chip-to-Chip connectivity, coupled with 2.5D-based ASIC integration experience for HBM2E based products.
OpenFive will continue to extend the series of Die-to-Die IP portfolio for other parallel PHY based architectures in the future as they become available.
OpenFive is a self-contained and autonomous custom silicon business unit of SiFive and offers customizable and differentiated SoC IP for Artificial Intelligence, Edge Computing, HPC, and Networking solutions. The OpenFive portfolio includes low-latency, high-throughput Interlaken connectivity fabric, 400/800G Ethernet, High-bandwidth memory (HBM2/E), USB subsystem IP, and die-to-die interconnect IP for next-generation heterogeneous chiplet-style products.
OpenFive’s end-to-end expertise in Architecture, Design Implementation, Software, Silicon Validation, and Manufacturing delivers high-quality silicon, with first-time-right results. For more information, please visit OpenFive.com.
SiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has 15 design centers worldwide and backing from Sutter Hill Ventures, SK hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures. For more information, please visit www.sifive.com.
SiFive & OpenFive
Hilary Livingston Castle
INK Communications for SiFive