Cadence Expands Chip Design Partnership With Samsung

<p><strong>SAN JOSE<&sol;strong> &&num;8212&semi; Cadence Design Systems has expanded its collaboration with Samsung Foundry to accelerate 3D-IC chip design&period; Through the continued collaboration&comma; the reference flow featuring the Cadence Integrity 3D-IC platform has been enabled to advance Samsung Foundry’s 3D-IC methodology&period; Using the Cadence platform&comma; customers creating complex&comma; next-generation hyperscale computing&comma; mobile&comma; automotive and AI applications can greatly optimize power&comma; performance and area &lpar;PPA&rpar; for each die&period;<&sol;p>&NewLine;<p>The PPA of a design can be impacted when chips are stacked in a 3D-IC configuration versus a 2D configuration due to the presence of large 3D structures like TSVs&comma; which connect the stacked chips&period; In addition to blocking standard cell placement area&comma; these structures block routing resources as well&period; The Cadence Integrity 3D-IC platform alleviates these traditional challenges&comma; letting users create multiple TSV insertion scenarios and devise an optimal 3D structure placement on a die with reduced wirelength penalties while boosting PPA and productivity&period; The platform also lets users perform 3D-IC design planning&comma; implementation and signoff from a single cockpit&comma; making the design process faster and easier&period;<&sol;p>&NewLine;<p>&OpenCurlyDoubleQuote;Customers creating stacked die designs at advanced nodes are always looking to make use of the benefits of our technologies without compromising PPA&comma;” said SangYun Kim&comma; vice president of the Foundry Design Technology Team at Samsung Electronics&period; &OpenCurlyDoubleQuote;The enablement that resulted from our collaboration with Cadence leverages advanced 3D-IC capabilities that provide our mutual customers with innovative techniques to build 3D designs without giving up PPA due to the additional structures introduced with multi-die stacking&period; After working with Cadence successfully on the 3D-IC system planning reference flow&comma; we are confident our customers can achieve their own unique design goals for multi-die stacked designs&period;”<&sol;p>&NewLine;<p>&OpenCurlyDoubleQuote;Through our latest collaboration with Samsung Foundry&comma; we’re enabling customers to circumvent the typical challenges that arise with 3D-IC design while optimizing PPA in parallel&comma;” said Vivek Mishra&comma; corporate vice president of the Digital and Signoff Group at Cadence&period; &OpenCurlyDoubleQuote;The Integrity 3D-IC platform brings together leading<i> <&sol;i>silicon and package implementation with system analysis<i> <&sol;i>capabilities&comma; helping designers improve overall productivity&period; By leveraging Samsung Foundry’s advanced 3D-IC capabilities and the Integrity 3D-IC platform&comma; our customers have access to an optimal solution for high-quality&comma; multi-die implementation&period;”<&sol;p>&NewLine;