AMD Introduces New Alveo Accelerator for Electronic Trading

<p><strong>SANTA CLARA<&sol;strong> &&num;8212&semi; <a title&equals;"" href&equals;"http&colon;&sol;&sol;www&period;amd&period;com&sol;" target&equals;"&lowbar;blank" rel&equals;"nofollow noopener"><u>AMD<&sol;u><&sol;a> has announced the <a title&equals;"" href&equals;"https&colon;&sol;&sol;www&period;amd&period;com&sol;en&sol;products&sol;accelerators&sol;alveo&sol;ul3422&period;html" target&equals;"&lowbar;blank" rel&equals;"nofollow noopener"><u>AMD Alveo UL3422 accelerator card<&sol;u><&sol;a>&comma; the latest addition to its family of accelerators designed for ultra-low latency electronic trading applications&period; AMD Alveo UL3422 provides trading firms&comma; market makers and financial institutions with a slim form factor accelerator optimized for rack space&comma; cost and designed for a fast path to deployment in a wide range of servers&period;<&sol;p>&NewLine;<p>The Alveo UL3422 accelerator is powered by an AMD Virtex UltraScale&plus; FPGA that features a novel transceiver architecture with hardened&comma; optimized network connectivity cores&comma; custom built for high-speed trading&period; It enables ultra-low latency trade execution&comma; achieving less than 3ns FPGA transceiver latency and breakthrough &OpenCurlyQuote;tick-to-trade&&num;8217&semi; performance not achievable with standard off-the-shelf FPGAs<sup>1<&sol;sup>&period;<&sol;p>&NewLine;<p>&OpenCurlyDoubleQuote;Speed is the ultimate advantage in the increasingly competitive world of high-speed trading&comma;” said Yousef Khalilollahi&comma; corporate vice president &amp&semi; general manager&comma; Adaptive Computing Group&comma; AMD&period; &OpenCurlyDoubleQuote;The Alveo UL3422 card provides a lower-cost entry point while still delivering cutting-edge latency performance&comma; making it accessible to firms of all sizes that want to stay competitive in the ultra-low latency trading space&period;”<&sol;p>&NewLine;<p><strong>New Slim Form Factor for Cost-Effective Deployment<&sol;strong><br &sol;>&NewLine;The Alveo UL3422 accelerator card is packaged in a slim FHHL &lpar;full height&comma; half length&rpar; form factor designed to fit into a wide range of servers and co-location exchange data centers&period;<&sol;p>&NewLine;<p>Compared to its predecessor&comma; the Alveo UL3422 accelerator reduces port density&comma; on-board memory&comma; and connectivity options&comma; while still being powered by the same AMD Virtex UltraScale&plus; VU2P FPGA for ultra-low latency&period;<&sol;p>&NewLine;<p>As a result&comma; the Alveo UL3422 is half the size with equivalent performance to the existing Alveo UL3524 accelerator card which holds the current STAC-T0 benchmark world record for tick-to-trade performance&period; The slim FHHL form factor of the Alveo UL3422 allows financial institutions to cost-effectively optimize compute density and rack-space&period;<&sol;p>&NewLine;<p><strong>Ecosystem Solutions and Fast Path to Trade<&sol;strong><br &sol;>&NewLine;The Alveo UL3422 accelerator card is designed for a fast path to deployment by utilizing available infrastructure ecosystem solutions and reference designs&comma; giving trading developers the edge they need for rapid design closure and time to market&period;<&sol;p>&NewLine;<p>It is supported by a growing network of ecosystem partner solutions that provide IP and development frameworks to enable the rapid implementation of trading solutions&period;<&sol;p>&NewLine;<ul>&NewLine;<li><a title&equals;"" href&equals;"https&colon;&sol;&sol;www&period;exegy&period;com&sol;" target&equals;"&lowbar;blank" rel&equals;"nofollow noopener"><u>Exegy<&sol;u><&sol;a>&comma; a provider of end-to-end&comma; front-office trading solutions&comma; is supporting the AMD Alveo UL3422 card with its Development Framework &lpar;nxFramework&rpar;&period; nxFramework is a hardware and software development environment designed to efficiently build and maintain ultra-low latency FPGA applications for the financial industry&period;<&sol;li>&NewLine;<li><a title&equals;"" href&equals;"https&colon;&sol;&sol;hypertec&period;com&sol;" target&equals;"&lowbar;blank" rel&equals;"nofollow noopener"><u>Hypertec<&sol;u><&sol;a>&comma; a provider of hardware&comma; cloud&comma; and value-added solutions for the financial services industry&comma; has closely collaborated with AMD&period; The company’s HF X410R-G6 server is certified to support the Alveo UL3422 accelerator&comma; making it the first 1U server fully optimized for this card&period;<&sol;li>&NewLine;<li><a title&equals;"" href&equals;"https&colon;&sol;&sol;www&period;xelera&period;io&sol;" target&equals;"&lowbar;blank" rel&equals;"nofollow noopener"><u>Xelera Technologies<&sol;u><&sol;a>&comma; a software provider for high-speed network technology and machine learning &lpar;ML&rpar; applications&comma; collaborated with AMD to help overcome the latency drawback of ML algorithms in high-frequency trading&period; With Xelera Silva users can take advantage of real-time&comma; ML-based trading decisions while leveraging XGBoost&comma; LightGBM&comma; CatBoost and other advanced models&period;<&sol;li>&NewLine;<&sol;ul>&NewLine;<p>The Alveo UL3422 supports traditional FPGA flows using the AMD Vivado Design Suite and comes with a suite of reference designs and performance benchmarks that allow FPGA designers to quickly explore key metrics and develop custom trading strategies to specification&period;<&sol;p>&NewLine;<p>AMD is also providing developers with the open-sourced and community-supported FINN development framework&comma; enabling low-latency AI models to be deployed into high-performance trading systems&period; FINN uses PyTorch and neural network quantization techniques designed to reduce the size of AI models while maintaining accuracy&period; The FINN compiler generates Quantized Neural Network &lpar;QNN&rpar; Hardware IP blocks that can be used with AMD FPGAs&period;<&sol;p>&NewLine;<p>The AMD Alveo UL3422 accelerator card is currently available and shipping in production volumes to global financial services customers&period;<&sol;p>&NewLine;

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